It is well known that in many scientific fields, a physical quantity of interest appears in the form of a time-varying voltage. Such signals may be observed on an oscilloscope or digitized and recorded with a computer for analysis and display. If the signal is repetitive with respect to some time, it may be advantageous to digitize and average the signal over several records. Each record is initiated by a trigger that is synchronized to the same time or phase in the repetitive signal. During each record the voltage waveform is sampled at periodic time intervals and the samples are digitized and stored in memory. Because the time spans and sampling intervals are identical for each record, the data from each record can be added to the sum of the previous records and the final result divided by the number of records to form the average. Such averaging can improve the signal-to-noise ratio. A measurement instrument particularly well suited for rapidly varying signals is a digital signal averager (DSA).
The digitization of the voltage signal at the input to the DSA is accomplished by an analog-to-digital converter (ADC). The digital resolution is determined by the number of bits in the ADC, and the minimum voltage quantization interval is the width of one least-significant-bit (LSB).
It is well known by those skilled in the art that the signal-to-noise ratio of the averaged signal improves in proportion to the square root of the number of records that are averaged, provided the noise is not time-correlated with the trigger. If the noise on the signal is less than 1 LSB of the ADC, then the accuracy of the averaged signal is limited by the size of 1 LSB.
The following example helps to explain the limitation on accuracy caused by the digital resolution of the ADC. A DSA designed for recording fast signals might have an input ADC capable of sampling at two (2) nanosecond intervals with a resolution of eight bits (256 discrete levels). For the convenience of calculation, assume that the eight bits of the ADC cover an input voltage range from 0 to 2.55 volts with the ADC output code 0 centered on zero volts and the output code 255 centered on 2.55 volts. Accordingly, the ADC output is some multiple of 0.01 volts. Therefore, if the analog signal amplitude at some particular time relative to the trigger is always 1.004 volts, the ADC will always record 1.00 volts when it samples that point in the waveform. Consequently, the waveform reconstructed from the ADC samples will not have a smooth, continuous shape, but will increase or decrease in abrupt steps of 0.01 volt. Relevant details of the waveform which are smaller than the 0.01 volt resolution of the ADC will be lost. The change in voltage corresponding to the change of the least-significant-bit of the ADC (0.01 volts in this example) is often termed the voltage bin width.
FIGS. 1 and 2 illustrate the loss of detail associated with the voltage bin width. FIG. 1 shows an analog input signal to the ADC. This signal meanders within the limits of two bins defined by the LSB boundaries at 1.005, 1.015, and 1.025 volts. The center of the lower bin is at 1.01 volts, and samples within this bin always generate the ADC code 101. The upper bin is centered at 1.02 volts, and samples within this bin always yield the ADC code 102. In this example, the ADC samples the analog input voltage at 2-nanosecond intervals, as denoted by the dots in FIGS. 1 and 2. FIG. 2 shows the digital output of the ADC resulting from the sampling of the analog voltage in FIG. 1. Dividing the ADC code by 100 expresses the digital output in terms of the input voltage. Clearly, the voltage variation details that fell within 1 LSB at the ADC input are lost in the digital output of the ADC.
Those skilled in the art will recognize that a standard solution to the limitations caused by the finite bin width involves the addition of noise to the signal, as illustrated in FIG. 3. In this example, the instantaneous input voltage at the sampling time is 1.008 volts. This falls within the amplitude bin defined by ADC code 101, which has bin boundaries at 1.005 volts and 1.015 volts. In the absence of added noise, this signal would be reported by the ADC as code 101, which represents a 1.010 input voltage. To achieve a more accurate measurement of the voltage, noise is artificially added to the signal. There are two critical requirements for the added noise. First, the noise must be random with respect to the trigger and the signal. Second, the noise must have a zero mean voltage. In this example, the noise has a uniform or flat distribution of amplitudes, as defined in FIG. 4. In this case, the width of the noise distribution, W, is set equal to the width of 1 LSB in the ADC. When the signal plus noise is sampled a large number of times, 80% of the samples will yield ADC code 101, and 20% of the samples will generate ADC code 100. Consequently, the average code will be: EQU (0.80.times.101)+(0.20.times.100)=100.8 (1)
which represents an input voltage of 1.008 volts.
While useful for explaining the theory, the flat noise distribution in FIG. 4 is impractical to implement. Prior art devices typically use the convenient Gaussian noise distribution depicted in FIG. 5. The root-mean-square (rms) noise voltage for this distribution has a value denoted by .sigma., and the Full Width at Half Maximum (FWHM) is given by: EQU FWHM=2.35.sigma. (2)
The typical distribution of Gaussian noise used in prior art devices is random with respect to the trigger and the signal to be digitized. Furthermore, it has a zero mean and a uniform power density versus frequency. Hereinafter, Gaussian noise having these characteristics will be referred to as "white Gaussian noise".
Because the Gaussian curve does not have a linear distribution, it is not necessarily obvious that replacing the flat noise distribution with white Gaussian noise will result in a measurement of the input voltage that is linearly accurate to a small fraction of 1 LSB. However, by calculating the maximum systematic error caused by the Gaussian noise in measuring the input voltage after averaging many samples, the linear accuracy can be proven. The maximum systematic error, .DELTA., occurs when the original signal (and the mean of the noise distribution) is half-way between the center and the edge of a voltage bin. As shown in FIG. 6, the systematic error becomes a negligible fraction of 1 LSB, when the rms voltage of the white Gaussian noise is greater than 0.6 LSB. To provide a margin of safety, .sigma..gtoreq.1 LSB is typically chosen for the noise amplitude. Under these conditions, the white Gaussian noise provides essentially the same quality of interpolation below 1 LSB in the averaged signal as is afforded by the flat noise distribution.
However, the example employing white Gaussian noise readily demonstrates how this traditional solution limits the speed of convergence to a precise answer. The added noise causes a random error in each sample of the input signal which can be reduced by averaging the data. The number of samples which must be averaged to achieve a desired precision in the measured voltage can be calculated as the square of the product of FWHM of the Gaussian noise and the inverse of the fraction of one LSB representing the desired precision. For example, where the FWHM of the Gaussian noise is two (2) LSB, to achieve a precision of 1/16 LSB in the measured voltage (2.times.16).sup.2, or 1024, samples must be averaged.
The discussion to this point has presumed an ADC with voltage bin widths which are perfectly uniform over the entire measurement range. This corresponds to zero differential non-linearity (DNL). However, a practical ADC has a finite differential non-linearity specification such as .+-.1/2 LSB. Taking the exemplary eight-bit ADC having an input voltage range of 0 to 2.55 volts, the voltage bin width is not a constant 0.01 volts, but can vary from 0.005 to 0.015 volts over the ADC range. To aid in understanding the errors caused by differential non-linearity, apply the earlier example of a uniform noise distribution to the case in FIG. 7. In FIG. 7, the voltage bin width for ADC code 101 is only 0.005 volts, while the width for code 100 is 0.015 volts. When the input signal plus the flat noise is sampled many times, 30% of the samples yield the 101 code and 70% of the samples return the 100 code. Thus, the computed average voltage for the input signal is: EQU (0.30.times.101)+(0.70.times.100)=100.3 (3)
which represents an input voltage of 1.003 volts. This result is in error of 0.005 volts in reference to the true value of 1.008 volts. The differential non-linearity has caused a 0.005-volt inaccuracy in the measurement. This underlying systematic error is independent of the number of samples averaged.
One method for correcting the differential non-linearity error is to trade some of the useful range of the ADC for a decrease in the systemic error attributable to the DNL. For example, by broadening the width of the flat noise distribution until it spans approximately 16 times the average width of 1 LSB, the added noise will average the measurement over 16 adjacent voltage bins. This reduces the differential non-linearity error by approximately a factor of 16 while giving up 16/256 or 6.25% of the useful ADC range. Systematic error from DNL becomes .+-.1/2 LSB.times.1/16, or .+-.1/32 LSB, after averaging many samples. Further improvement can be gained by using an even wider noise distribution with a corresponding reduction in the useful range of the ADC.
The uniform noise distribution in the previous paragraph has an rms voltage given by: ##EQU1## Consequently, the same functionality could be achieved by replacing the uniform noise with white Gaussian noise having the same value of .sigma., i.e., 4.6 LSB. This corresponds to an FWHM of 10.8 LSB for the Gaussian distribution. Such a solution raises a serious problem. Adding the Gaussian noise causes a random error of 10.8 LSB (FWHM) in a single sample of the voltage. To reduce this error to 1/16 LSB requires averaging (10.8.times.16).sup.2 =29,860 samples of the input signal. Clearly, the rate of convergence to a precision and accuracy of 1/16 LSB is extremely slow with the prior art method of adding noise.
Another solution to the DNL error problem was solved by Gatti et al. for the field of pulse height analysis (C. Cottini, E. Gatti, and V. Svelto, Nucl. Instr. and Meth. 24 (1963) 241). Gatti employed a circuit generating offsets which incremented by the average bin width of one LSB, known as a Gatti slider. Although not originally designed for use in a digital signal averager, the Gatti slider concept can be modified and advantageously applied to a digital signal averager as follows. The result is a more efficient method for reducing differential non-linearity. A series of measurements are taken where the analog input signal is slid across a predetermined number of average bin widths by adding an analog voltage offset to the input signal. The analog voltage offset corresponds to a whole number multiple of the average voltage bin width and is incremented with each record. The summed analog signal is digitized and the results are averaged. Accordingly, the error introduced as a result of the differential non-linearity of the voltage bin width is reduced by the factor corresponding to the number of voltage bins across which the summed analog signal is averaged.
Other devices have been previously disclosed. Typical of the art are those devices disclosed in the following U.S. patents:
______________________________________ U.S Pat. No. Inventor(s) Issue Date ______________________________________ 4,490,806 Enke et al. Dec. 25, 1984 4,393,372 W. Hoehn Jul. 12, 1983 4,144,577 G. Ley Mar. 13, 1979 3,622,765 W. Anderson Nov. 23, 1971 ______________________________________
The U.S. Pat. No. 4,490,806 discloses a high speed data acquisition which includes a noise source for improving the dynamic range in the summed time spectra. The amplitude of the added noise is at least as large as one LSB of the ADC.
The U.S. Pat. No. 3,622,765 discloses a means for adding sub-LSB (SLSB) analog increments to the analog signal before digitizing in the ADC. The resulting digital waveforms are summed or averaged over repeated scans. The analog increments are derived from a repetitive, continuous, incremental waveform, producing N discrete increments. The '765 device does not compensate for the differential non-linearity of the ADC. Furthermore, the '765 device does not disclose a method of adding discrete, non-linear increments for reducing the error when averaging a number of records which is less than N.
The U.S. Pat. No. 4,144,577 discloses a device employing the method described in the '765 patent. The interpolation step size is intended to be less than one LSB of the ADC. As with the '765 device, no compensation is made for the differential non-linearity of the ADC. Similarly, the '577 patent does not teach a device which permits the addition of discrete, non-linear increments for error reduction when sampling less than the optimum number of samples, N.
The U.S. Pat. No. 4,393,372 discloses a device for increasing the number of bits by one in a flash ADC encoding an analog signal. The method adds .+-.1/2 LSB and -1/2 LSB of analog voltage to the input signal on alternate samples of the input signal. The '372 device embodied in discrete components is not designed for interpolating to less than 1/2 LSB. Furthermore, the '372 device does not compensate for the differential non-linearity of the ADC.
The '806, '372, '577, and '765 prior art devices do not correct for errors introduced by the differential non-linearity of the ADC. As a result, the prior art devices do not work accurately for all ADC codes. Additionally, the '372, '577, and '765 prior art devices disclose only the addition of linear increments or increments derived from a digital waveform of alternating polarity. Such a practice causes deterioration of accuracy when the number of records obtained is not a whole-number multiple of the number of increments in the complete set of increments.
Thus, it is an object of the present invention to provide a method for improving the accuracy of an averaged signal when the noise inherent in the signal is not large compared to 1 LSB, and to converge to the desired level of accuracy more rapidly than is possible with prior art.
Another object of the present invention is to provide a method for reducing the differential non-linearity of the ADC so that the interpolation to a fraction of 1 LSB is accurate for all ADC codes.
A still further object of the present invention is to provide a method for producing results which are more precise and more accurate in a given measurement time than is possible with the noise-adding prior art, and wherein a means is provided to obtain a faster solution for interpolating to a fraction of 1 LSB, and a faster solution for reducing the error caused by the differential non-linearity of the ADC in the DSA.
Yet another object of the present invention is to provide a method wherein non-linear increments can be utilized to permit greater accuracy when the number of records obtained does not permit the complete set of increments to be employed.